AD8158 datasheet(16/36 Pages) AD

16 / 36 page

AD8158

Rev. 0 | Page 16 of 36

Table 7. Register Address 0x0F

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Function

Set to 0

MODE[1]

MODE[0]

Mode

Table 8. Setting the Control Interface Mode

Mode 1

Mode 0

Control Mode

Pin control

Mixed control

Serial control

THE SWITCH

(MUX/DEMUX/UNICAST/BICAST/LOOPBACK)

The mux and demux functions of the AD8158 can be controlled

either with the toggle pins or through the register map. The

multiplexer path switches received data from Input Port A or

Input Port B to Output Port C. The SEL[3:0] pins allow switching

lanes independently. The demultiplexer path switches received

data from Input Port C to Output Port A, Output Port B, or (if

bicast mode is enabled) to both Output Port A and Output Port B.

Table 9. Port Selection and Configuration with All

Loopbacks Disabled

BICAST

SELx

Output

Port A

Output

Port B

Output

Port C

Ix_C[3:0]

Idle

Ix_A[3:0]

Idle

Ix_C[3:0]

Ix_B[3:0]

Ix_C[3:0]

Ix_A[3:0]

Ix_C[3:0]

Ix_B[3:0]

When the device is in unicast mode, the output lanes on either

Port A or Port B are in an idle state. In the idle state, the output

tail current is set to 0, and the P and N sides of the lane are

pulled up to the output termination voltage through the on-chip

termination resistors. To save power, the unused receiver

automatically disables.

The AD8158 supports port-level loopback, illustrated in Figure 36.

The loopback control pins override the lane select (SEL[3:0])

and bicast control (BICAST) pin settings at the port level. In serial

control mode, Bits [6:4] of Register 0x01 control loopback and

are equivalent to asserting Pin LB_A, Pin LB_B, and Pin LB_C.

Table 10 summarizes the different loopback configurations.

The loopback feature is useful for system debug, self test, and

initialization, allowing system ASICs to compare Tx and Rx

data sent over a single bidirectional link. Loopback can also be

used to configure the device as a 4- to 12-lane receive equalizer

or backplane redriver.

1:2 DEMUX

Ox_A[3:0]

Ox_B[3:0]

Ix_B[3:0]

Ix_A[3:0]

PORT C LOOPBACK

PORT A LOOPBACK

PORT B LOOPBACK

2:1 MUX

Ix_C[3:0]

Ox_C[3:0]

Figure 36. Port Level Loopback

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