CC2430 datasheet(49/212 Pages) TAOS

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CC2430

8051 CPU : Interrupts

CC2430 Data Sheet (rev. 2.1) SWRS036F

Page 49 of 211

Table 29: Instructions that affect flag settings

Instruction

ADD

ADDC

SUBB

MUL

DIV

RRC

RLC

SETB C

CLR C

CPL C

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

CJNE

“0”=set to 0, “1”=set to 1, “x”=set to 0/1, “-“=not affected

11.5

Interrupts

The CPU has 18 interrupt sources. Each

source has its own request flag located in a set

of Interrupt Flag SFR registers. Each interrupt

requested by the corresponding flag can be

individually

enabled

disabled.

The

definitions of the interrupt sources and the

interrupt vectors are given in Table 30.

The interrupts are grouped into a set of priority

level groups with selectable priority levels.

The interrupt enable registers are described in

section 11.5.1 and the interrupt priority settings

are described in section 11.5.3 on page 57.

11.5.1

Interrupt Masking

Each interrupt can be individually enabled or

disabled by the interrupt enable bits in the

Interrupt Enable SFRs IEN0, IEN1 and IEN2.

The CPU Interrupt Enable SFRs are described

below and summarized in Table 30.

Note that some peripherals have several

events that can generate the interrupt request

associated with that peripheral. This applies to

Port 0, Port 1, Port 2, Timer 1, Timer2, Timer

3, Timer 4 and Radio. These peripherals have

interrupt mask bits for each internal interrupt

source in the corresponding SFR registers.

In order to enable any of the interrupts in the

CC2430, the following steps must be taken:

1. Clear interrupt flags

2. Set individual interrupt enable bit in

the peripherals SFR register, if any.

3. Set

the

corresponding

individual,

interrupt enable bit in the IEN0, IEN1

or IEN2 registers to 1.

4. Enable global interrupt by setting the

EA bit in IEN0 to 1

5. Begin the interrupt service routine at

the corresponding vector address of

that interrupt. See Table 30 for

addresses

Figure 10 gives a complete overview of all

interrupt sources and associated control and

state registers. Shaded boxes are interrupt

flags that are automatically cleared by HW

when interrupt service routine is called.

indicates a one-shot, either due to the level

source or due to edge shaping. For the

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