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CC2430 Datasheet(PDF) 77 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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CC2430 Datasheet(HTML) 77 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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77 / 212 page  CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 77 of 211 FCTL (0xAE) – Flash Control Bit Name Reset R/W Description 7 BUSY 0 R Indicates that write or erase is in operation 0 No write or erase operation active 1 Write or erase operation activated 6 SWBSY 0 R Indicates that current word write is busy; avoid writing to FWDATA register while this is true 0 Ready to accept data 1 Busy 5 - 0 R/W Not used. 4 CONTRD 0 R/W Continuous read enable mode 0 Avoid wasting power; turn on read enables to flash only when needed 1 Enable continuous read enables to flash when read is to be done. Reduces internal switching of read enables, but greatly increases power consumption. 3:2 0 R/W Not used. 1 WRITE 0 R0/W Write. Start writing word at location given by FADDRH:FADDRL . If ERASE is set to 1, a page erase of the whole page addressed by FADDRH, is performed before the write. 0 ERASE 0 R0/W Page Erase. Erase page that is given by FADDRH[6:1] FWDATA (0xAF) – Flash Write Data Bit Name Reset R/W Description 7:0 FWDATA[7:0] 0x00 R/W Flash write data. Data written to FWDATA is written to flash when FCTL.WRITE is set to 1. FADDRH (0xAD) – Flash Address High Byte Bit Name Reset R/W Description 7 - 0 R/W Not used 6:0 FADDRH[6:0] 0x00 R/W Page address / High byte of flash word address Bits 6:1 will select which page to access. FADDRL (0xAC) – Flash Address Low Byte Bit Name Reset R/W Description 7:0 FADDRL[7:0] 0x00 R/W Low byte of flash word address FWT (0xAB) – Flash Write Timing Bit Name Reset R/W Description 7:6 - 00 R/W Not used 5:0 FWT[5:0] 0x2A R/W Flash Write Timing. Controls flash timing generator. 13.4 I/O ports The CC2430 has 21 digital input/output pins that can be configured as general purpose digital I/O or as peripheral I/O signals connected to the ADC, Timers or USART peripherals. The usage of the I/O ports is fully configurable from user software through a set of configuration registers. The I/O ports have the following key features: |
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