CC2430 datasheet(79/212 Pages) TAOS

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CC2430

Peripherals : I/O ports

CC2430 Data Sheet (rev. 2.1) SWRS036F

Page 79 of 211

nibble have their individual interrupt enables.

For the P2_0 – P2_4 inputs there is a common

interrupt enable.

When an interrupt condition occurs on one of

the

general

purpose

I/O

pins,

the

corresponding interrupt status flag in the P0-

P2 interrupt flag registers, P0IFG , P1IFG or

P2IFG

will be set to 1. The interrupt status flag

is set regardless of whether the pin has its

interrupt enable set. When an interrupt is

serviced the interrupt status flag is cleared by

writing a 0 to that flag, and this flag must be

cleared prior to clearing the CPU port interrupt

flag (PxIF).

The I/O SFR registers used for interrupts are

described in section 13.4.9 on page 82. The

registers are summarized below:

•

P1IEN

: P1 interrupt enables

•

PICTL

: P0/P2 interrupt enables and P0-2

edge configuration

•

P0IFG

: P0 interrupt flags

•

P1IFG

: P1 interrupt flags

•

P2IFG

: P2 interrupt flags

13.4.5

General Purpose I/O DMA

When used as general purpose I/O pins, the

and P1 ports are each associated with one

DMA trigger. These DMA triggers are IOC_0

for P0 and IOC_1 for P1 as shown in Table 41

on page 94.

The IOC_0 or IOC_1 DMA trigger is activated

when an input transition occurs on one of the

or P1 pins respectively. Note that input

transitions on pins configured as general

purpose I/O inputs only will produce the DMA

trigger.

Note that port registers P0 and P1 are mapped

to XDATA memory space (see Table 24 on

page 35). Therefore these registers are

reachable for DMA transfers. Port register P2

is not reachable for DMA transfers.

13.4.6

Peripheral I/O

This section describes how the digital I/O pins

are configured as peripheral I/Os. For each

peripheral unit that can interface with an

external system through the digital input/output

pins, a description of how peripheral I/Os are

configured is given in the following sub-

sections.

In general, setting the appropriate PxSEL bits

to 1 is required to select peripheral I/O function

on a digital I/O pin.

Note that peripheral units have two alternative

locations for their I/O pins, refer to Table 40.

Also note that as a general rule only two

peripherials can be used per IO Port at a time.

Priority can be set between these if conflicting

settings regarding IO mapping is present.

Priority among unlisted peripherial units is

undefined

and

should

not

used

(P2SEL.PRIxP1 and P2DIR.PRIP0 bits). All

combinations not causing conlicts can be

combined.

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