M66596FP datasheet(42/131 Pages) RENESAS

42 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 42 of 127

2.13 DCP configuration

When data communication is being carried out using control transfers, the default control pipe should be used.

DCP configuration register [DCPCFG]

<Address: 5CH>

CNTMD

DIR

Bit

Name

Function

S/W

H/W

Note

15-9 Nothing is placed here. These should be fixed at “0”.

CNTMD

Continuous transfer mode

0: Non-continuous transfer mode

1: Continuous transfer mode

R/W

3.4.1

*1)

7-5 Nothing is placed here. These should be fixed at “0”.

DIR

Transfer direction

Control transfer direction in the host mode.

0: Receiving (Control read data stage and

Control write status stage)

1: Sending (Control write data stage and

Control read status stage)

R/W

3.6.1

*2)

7-0 Nothing is placed here. These should be fixed at “0”.

<<Notes>>

*1) Because the DCP buffer memory is used for both control read transfers and control write transfers, the CNTMD

bit will serve as the bit common to both, regardless of the transfer direction.

*2) This bit should be set to “0” in the peripheral mode.

DCP maximum packet size register [DCPMAXP]

<Address: 5EH>

DEVSEL

MXPS

Bit

Name

Function

S/W

H/W

Note

15-14 DEVSEL

Device select

This specifies the device adress for the DCP at

Host mode.

00 : Address 0

01 : Address 1

02 : Address 2

03 : Address 3

R/W

3.6.1

*3)

13-7 Nothing is placed here. These should be fixed at “0”.

6-0 MXPS

Maximum packet size

This specifies the maximum packet size for the

DCP.

R/W

3.3

*4)

<<Notes>>

*3) This bit should be set “00” in the peripheral mode.

*4) This should not be set to anything other than the USB specification. Also, because b2-b0 bits are fixed at “0”,

writing to these is invalid.

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