M66596FP datasheet(33/131 Pages) RENESAS

33 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 33 of 127

2.7.1

Interrupt masks

The VBSE, RSME, SOFE, DVSE, CTRE, BEMPE, NRDYE, and BRDYE bits of the INTENB0 register and BCHGE,

DTCHE,

SIGNE, SACKE

of INTENB1 register operate as interrupt mask bits. Each of the bits should be used

to specify whether interrupt signal output is enabled or disabled for the INT_N pin.

The BRDYENB register, NRDYENB register and BEMPENB register operate as the BRDY interrupt mask bit,

the NRDY interrupt mask bit, and the BEMP interrupt mask bit, respectively, for the each corresponding pipe.

2.7.2

Device state transition interrupts

The URST, SADR, SCFG, and SUSP bits of the INTENB0 register operate as interrupt mask bits for the device

state transition interrupt (DVST). If a factor is disabled, no device state transition interrupt is issued in

response to the pertinent factor. However, the device state (DVSQ) transits in keeping with the circumstances.

This function is effective only at the time of a peripheral mode.

2.7.3

Control transfer stage transition interrupts

The WDST, RDST, CMPL and SERR bits of the INTENB0 register should be used to set the interrupt factors

for the control transfer stage transition interrupt (CTRT). If a factor is disabled, no control transfer stage

transition interrupts are issued in response to the pertinent factor.

This function is effective only at the time of a peripheral mode.

2.7.4

USB bus change interrupt

Interruption can be generated when a USB bus state changes. This interruption enable with the BCHGE bit of

INTENB1

signal in the Host mode. Please do not enable interruption during communication (at the time of "UACT=1"

setup). The bus change interruption is generated whichever it has chosen of Host and Peripheral mode.

2.7.5

Full-Speed detach detect interrupt

When Host mode, interruption can be generated when peripheral device is detached at the time of Full-Speed

mode. This interruption enable with the DTCHE bit of INTENB1 register.

2.7.6

Setup transaction error detect interupt

Interruption can be generated when the ACK packet from peripheral device isn’t able to be received at the

time of sending setup transaction at Host mode. This interruption enable with the SIGN bit of INTENB1 register.

2.7.7

Setup transaction complete interrupt

Interruption can be generated when the ACK packet from peripheral device is received at the time of sending

setup transaction at Host mode. This interruption enable with the SACKE bit of INTENB1 register.

2.7.8

Operations in the low-power sleep state

The VBSE, RSME, BCHG interrupts are generated in the low-power sleep state as well..

M66596FP Datasheet(PDF) 33 Page - Renesas Technology Corp

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