M66596FP datasheet(20/131 Pages) RENESAS

20 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 20 of 127

2.3.3

Line status monitor

Table 2.4Table 2.3 shows the USB data bus line statuses of the controller. The controller monitors the line

status (D+ line and D- line) of the USB data bus using the LNST bit of the SYSSTS register. The LNST bit is

configured of two bits. For the meaning of each of the bits, please refer to the table below.

The line status is checked with the Full-Speed receiver inside a M66596. This controller controls a Full-Speed

receiver automatically when internal clock is supplied. If the FSRPC of the SYSCFG register is set up, it is

enabled by setting the FSRPC of the SYSCFG register by S/W when internal clock is not supplied. After H/W

reset, in checking the state of D+ and D- before supplying an internal clock, please set a FSRPC bit as 1. Once

supplying an internal clock, it is not necessary to set up by S/W.

In the low-power sleep state, the line status cannot be monitored.

Table 2.4 USB data bus line statuses

LNST [1]

LNST [0]

During Full-Speed

operation

During Hi-Speed operation

During chirp operation

SE0

Squelch

J State

not Squelch

Chirp J

K State

Invalid

Chirp K

SE1

Invalid

Chirp:

The reset handshake protocol is being executed in the Hi-Speed operation enabled state (HSE = “1”).

Squelch:

SE0 or Idle state

not Squelch: Hi-Speed J state or Hi-Speed K state

Chirp J:

Chirp J state

Chirp K:

Chirp K state

2.3.4

USB data bus register control

A setup about resistance of a USB data bus is shown in Table 2.5. USB data bus line resistors are controled by

DMRPD

and DPRPU bit of SYSCFG register.

Table 2.5 Resistance control of a USB data bus

DMRPD

DPRPU

D-

D+

note

Open

Pull-Up

Peripheral Controller

Pull-Down

Host Controller

Pull-Down

Pull-Up

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