M66596FP datasheet(80/131 Pages) RENESAS

80 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 80 of 127

3.4.2

FIFO port functions

Table 3.16 shows the settings for the FIFO port functions of the controller. When data writing is being

accessed, writing data until the buffer is full (or the maximum packet size for non-continuous transfers)

automatically enables sending of the data. To enable sending of data before the buffer is full (or before the

maximum packet size for non-continuous transfers), the BVAL bit of the C/DxFIFOCTR register (or the DEND

signal when using DMA transfers) must be set to end the writing. Also, to send a Zero-Length packet, the BCLR

bit of the same register must be used to clear the buffer and then the BVAL bit set in order to end the writing.

When accessing reading, reception of new packets is automatically enabled if all of the data has been read.

However, data cannot be read when a Zero-Length packet is being received (DTLN=0), so the BCLR bit of the

DTLN

bit of the C/DxFIFOCTR register.

Table 3.16 FIFO port function settings

Bit name

Function

Reference

Note

REW

Buffer memory rewind (re-read, re-write)

3.4.4.2

DCLRM

Automatically clears data received for a specified

pipe after the data has been read

3.4.1.2

3.4.3.5

For DxFIFO

only

DMA transfer

assumed

DREQE

Asserts DREQ signal

3.4.3

For DxFIFO

only

MBW

FIFO port access bit width

3.4.2.1

TRENB

Enables transaction counter operation

3.4.2.5

For DxFIFO

only

TRCLR

Clears the current number of transactions

3.4.2.5

For DxFIFO

only

DEZPM

Zero-Length packet addition mode

3.4.3.3

For DMA only

C/DxFIFOSEL

ISEL

FIFO port access direction

3.4.2.1

For DCP only

BVAL

Ends writing to the buffer memory

3.4.2.4

3.4.2

BCLR

Clears the buffer memory on the CPU side

3.4.1.2

C/DxFIFOCTR

DTLN

Confirms the length of received data

3.4.2

DxFIFOTRN

TRNCNT

Sets the received transaction count

3.4.2.5

For DxFIFO

only

TGL

CPU / SIE buffer toggle

3.4.2.3

For CFIFO only

CFIFOSIE

(excluding

DCP)

SCLR

Clears the buffer memory on the SIE side

3.4.2.4

For CFIFO only

External pin

DEND

Ends writing to the buffer memory

3.4.3.4

For DMA

transfer only

3.4.2.1 FIFO port selection

Table 3.17 shows the pipes that can be selected with the various FIFO ports. The pipe to be accessed is

selected using the CURPIPE bit of the C/DxFIFOSEL register. After the pipe has been selected, “FRDY=1” should

be confirmed before accessing the FIFO port.

Also, the bus width to be accessed should be selected using the MBW bit. The buffer memory access direction

conforms to the DIR bit of the PIPExCFG register. However, the ISEL bit determines this only for the DCP.

Table 3.17 FIFO port access categorized by pipe

Pipe

Access method

Port that can be used

DCP

CPU access

CFIFO port register

CPU access

CFIFO port register

DxFIFO port register

PIPE1~PIPE7

DMA access

DxFIFO port register

M66596FP Datasheet(PDF) 80 Page - Renesas Technology Corp

M66596FP Datasheet(HTML) 80 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL