M66596FP datasheet(70/131 Pages) RENESAS

70 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 70 of 127

3.2.8

Frame refresh interrupt

Figure 3.18 shows an example of the SOFR interrupt output timing of the controller.

In the Host mode, the SOFR interrupt is generated when the frame number is refreshed,

In the Peripheral mode, the SOFR interrupt is generated, when the frame number is refreshed, or a damaged SOF

packet is detected. The interrupt operation should be specified using the SOFRM bit of the FRMNUM register.

(1) When “SOFRM=0” is selected

The SOFR interrupt is generated at the timing at which the frame number is refreshed (intervals of

approximately 1 ms). Interrupts are generated by the internal interpolation function even if an SOF packet is

damaged or missing. During Hi-Speed communication as well, interrupts are generated at the timing at which

the frame number is refreshed (intervals of approximately 1 ms).

(2) When “SOFRM=1” is selected

The SOFR interrupt is generated when SOF packets are damaged and when they are missing. During Hi-Speed

communication, the interrupt is generated only if the first packet of a uSOF packet with the same frame number

is damaged or missing.

(Corrupted and missing SOFs are recognized by the SOF interpolation function. For detailed information, please

refer to Chapter 0, SOF interpolation function.)

* SOFRM bit should not be set “SFRM=1” in the Host mode.

In the Peripheral mode, if the controller detects a new SOF packet during Full-Speed operation, it refreshes the

frame number and generates an SOFR interrupt. However, if the system does not enter the

µSOF lock state during

Hi-Speed operation, the frame number is not refreshed, and no SOFR interrupt is generated. Also, the SOF

interpolation function is not activated. The

µSOF lock state is the state in which uSOF packets with different frame

numbers are received twice in succession without an error occurring .

The conditions under which

µSOF lock monitoring begins, and under which µSOF lock monitoring stops, are as

noted below.

(1)

Conditions under which

µSOF lock monitoring begins

USBE=1 and the internal clock (SCKE) is being supplied

(2)

Conditions under which

µSOF lock monitoring stops

USBE=0 (S/W reset) or a USB bus reset is received, or a suspended state is detected

Peripheral Device

uSOF packet

uSOF number

Frame number

SOFR interrupt

(SOFRM=0)

(SOFRM=1)

uSOF Lock

uSOF packet

uSOF number

SOFR interrupt

uSOF lock

701

SOF interpolation, missing

Not locked

SOF interpolation

123

SOF interpolation function

SOF missing

SOF interpolation

Figure 3.18 Example of SOFR interrupt output timing

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