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M66596FP Datasheet(PDF) 106 Page - Renesas Technology Corp |
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M66596FP Datasheet(HTML) 106 Page - Renesas Technology Corp |
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106 / 131 page  M66596FP/WG rev .1.00 2006.3.14 page 106 of 127 4.9 Timing diagrams Table 4.1 Index for register access timing diagram Bus specification access R/W INDEX Note Separate bus CPU WRITE 4.9.1.1 CPU bus 0 Separate bus CPU READ 4.9.1.2. CPU bus 0 Multiplex bus CPU WRITE 4.9.2.1. CPU bus 0 Multiplex bus CPU READ 4.9.2.2 CPU bus 0 Table 4.2 Index for FIFO port access Access Bus I/F specifications *2) I/F specifications when operating DFORM OBUS R/W Note INDEX CPU CPU bus 0 Separate bus - WRITE - 4.9.1.1 CPU CPU bus 0 Separate bus - READ - 4.9.1.2. CPU CPU bus 0 Multiplex bus - WRITE - 4.9.2.1. CPU CPU bus 0 Multiplex bus - READ - 4.9.2.2 DMA CPU bus 2 ACK+RD/WR 010 WRITE Cycle steal transfer 4.9.3.1 *1) DMA CPU bus 2 ACK+RD/WR 010 READ Cycle steal transfer 4.9.3.2 *1) DMA SPLIT bus 1 ACK+STB 110 1 WRITE Cycle steal transfer 4.9.3.3 *1) DMA SPLIT bus 1 ACK+STB 110 1 READ Cycle steal transfer 4.9.3.4 *1) DMA SPLIT bus 1 ACK+STB 110 0 WRITE Cycle steal transfer 4.9.3.3 *1) DMA SPLIT bus 1 ACK+STB 110 0 READ Cycle steal transfer 4.9.3.5 *1) DMA CPU bus 1 Separate bus 000 WRITE Cycle steal transfer 4.9.3.6 DMA CPU bus 1 Separate bus 000 READ Cycle steal transfer 4.9.3.7 DMA SPLIT bus 2 ACK only 100 1 WRITE Cycle steal transfer 4.9.3.8 *1) DMA SPLIT bus 2 ACK only 100 1 READ Cycle steal transfer 4.9.3.9 *1) DMA SPLIT bus 2 ACK only 100 0 WRITE Cycle steal transfer 4.9.3.8 *1) DMA SPLIT bus 2 ACK only 100 0 READ Cycle steal transfer 4.9.3.10 *1) DMA CPU bus 3 ACK only 011 WRITE Cycle steal transfer 4.9.3.11 *1) DMA CPU bus 3 ACK only 011 READ Cycle steal transfer 4.9.3.12 *1) DMA CPU bus 2 Multiplex bus 000 WRITE Cycle steal transfer 4.9.4.1 DMA CPU bus 2 Multiplex bus 000 READ Cycle steal transfer 4.9.4.2 DMA CPU bus 1 ACK+RD/WR 010 WRITE Burst transfer 4.9.5.1 *1) DMA CPU bus 1 ACK+RD/WR 010 READ Burst transfer 4.9.5.2 *1) DMA SPLIT bus 1 ACK+STB 110 1 WRITE Burst transfer 4.9.5.3 *1) DMA SPLIT bus 1 ACK+STB 110 1 READ Burst transfer 4.9.5.4 *1) DMA SPLIT bus 1 ACK+STB 110 0 WRITE Burst transfer 4.9.5.3 *1) DMA SPLIT bus 1 ACK+STB 110 0 READ Burst transfer 4.9.5.5 *1) DMA CPU bus 2 Separate bus 000 WRITE Burst transfer 4.9.5.6 DMA CPU bus 2 Separate bus 000 READ Burst transfer 4.9.5.7 DMA SPLIT bus 2 ACK only 100 1 WRITE Burst transfer 4.9.5.8 *1) DMA SPLIT bus 2 ACK only 100 1 READ Burst transfer 4.9.5.9 *1) DMA SPLIT bus 2 ACK only 100 0 WRITE Burst transfer 4.9.5.8 *1) DMA SPLIT bus 2 ACK only 100 0 READ Burst transfer 4.9.5.10 *1) DMA CPU bus 3 ACK only 011 WRITE Burst transfer 4.9.5.11 *1) DMA CPU bus 3 ACK only 011 READ Burst transfer 4.9.5.12 *1) DMA CPU bus 1 Multiplex bus 000 WRITE Burst transfer 4.9.6.1 DMA CPU bus 1 Multiplex bus 000 READ Burst transfer 4.9.6.2 *1) Because the address signal is not used, the timing will be the same for the separate bus and multiplex bus. *2) The reading and writing timing are carried out using control signal. If the control signal is configured of a combination of multiple signals, the ratings from the falling edge will be valid starting from when the active delay signal changes. The ratings from the rising edge will be valid starting from the change in signals that become inactive more quickly. |
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