M66596FP datasheet(124/131 Pages) RENESAS

124 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 124 of 127

4.9.5.11 DMA Burst transfer write timing (CPU bus address not used: DFORM=011)

tdis (CTRLH - Dreq)

tw (CTRL_B)

tsu (D) th (D)

DREQi_N

(i=0,1)

D15-D0

tsu (Dend) th (Dend)

DENDi_N

(i=0,1)

trec (CTRL_B)

tw (cycle)

DACKi_N

(i=0,1)

17 tdis (CTRL - Dreq)

4.9.5.12 DMA burst transfer read timing (CPU bus address not used: DFORM=011)

tdis (CTRL - Dreq)

tw (CTRL_B)

ta (CTRL - D)

tv (CTRL - D)

DREQi_N

(i=0,1)

DACKi_N

(i=0,1)

D15-D0

ta (CTRL - DendV)

tv (CTRL - DendV)

DENDi _N

(i=0,1)

trec (CTRL_B)

tw (cycle)

Dn-1

Note 5-6

Note 5-1: The control signal when writing data is a combination of DACKi_N(i=0, 1), WR0_N and WR1_N.

Note 5-2: The control signal when reading data is a combination of DACKi_N and RD_N.

Note 5-3: The control signal when writing data is a combination of DACK0 and DSTRB0_N.

Note 5-4: The control signal when writing data is a combination of CS_N, WR0_N and WR1_N.

Note 5-5: The control signal when reading data is a combination of CS_N and RD_N.

Note 5-6: When the receipt data is one byte, the data determined time is "(23)td(DREQ-DV)" and the DEND determined

time is "(24)td(DREQ-DendV)".

Note 5-7: RD_N, WR0_N and WR1_N should not be timed to fall at the same time that CS_N is rising. Similarly, CS_N

should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the instances noted

above, an interval must be needed at least 10ns.

Note 5-8:. RD_N, WR0_N and WR1_N should not be timed to fall at the same time that DACKi_N is rising. Similarly,

DACKi_N should not be timed to fall at the same timing that RD_N, WR0_N and WR1_N are rising. In the

instances noted above, an interval must be needed at least 10ns.

M66596FP Datasheet(PDF) 124 Page - Renesas Technology Corp

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