SH7261 datasheet(337/1348 Pages) RENESAS

337 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 305 of 1312

REJ09B0320-0200

Section 11 Direct Memory Access Controller (DMAC)

The DMA controller (hereafter DMAC) is a module that handles high-speed data transfer without

CPU intervention in response to requests from software, on-chip peripheral I/O modules, or

external pins (external modules). The DMAC itself does not distinguish between requests from

on-chip peripheral I/O or external pins (external modules). The DMA supports data transfer

between memory units, memory and I/O modules, and I/O modules.

11.1

Features

• Channel number: Up to eight channels (with four channels capable of external requests)

• Transfer requests: Requests from 38 sources including software trigger, on-chip peripheral I/O,

and external pins (external modules)

• Maximum transfer bytes: 64 Mbytes

• Address space: 4 Gbytes

• Transfer data sizes:

 Single data transfer: 8, 16, 32, 64, and 128 bits

 Single operand transfer: 1, 2, 4, 8, 16, 32, 64, and 128 data

 Non-stop transfer: Up to the byte count "0"

• Transfer mode:

 Cycle-stealing transfer (dual-address transfer)

 Pipelined transfer (dual-address transfer)

• Maximum transfer speed:

 Cycle-stealing transfer: Minimum of three clock cycles per unit data transfer

 Pipelined transfer: Minimum of one clock cycle per unit data transfer

• Transfer conditions:

 Unit operand transfer: a single sequence of single operand data transfer in response to a

DMA request

 Sequential operand transfer: single operand transfers are repeated until the byte count

reaches "0"

 Non-stop transfer: data is continuously transferred until the byte count reaches "0" in

response to a single DMA request

• Channel priority:

Channel 0

> channel 1 > → > channel 6 > channel 7 (this priority order is fixed)

SH7261 Datasheet(PDF) 337 Page - Renesas Technology Corp