SH7261 datasheet(344/1348 Pages) RENESAS

344 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 312 of 1312

REJ09B0320-0200

11.3.1

DMA Current Source Address Register (DMCSADR)

DMCSADR is a register used to specify the start address of the transfer source.

The value in this register is transferred to the working source-address register at the start of DMA

transfer.

The default behavior is for the contents of the working source-address register to be returned on

completion of single operand transfer. However, the contents of the working source address

= 011) is made for the

source address and when the source-address reload function is enabled. In the latter case, the

contents of the DMA reload source address register (DMRSADRn) are returned to this register on

completion of DMA transfer.

This register must be set before transfer is initiated, regardless of whether the reload function is

enabled or disabled.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

—

R/W

—

R/W

CSA

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

CSA

Undefined

R/W

Holds source address bits A31 to A0

Notes: 1. Set this register so that DMA transfer is performed within the correctly aligned address

boundaries for the transfer sizes listed below.

• When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".

• When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).

2. Only write to this register when single operand transfer is not in process on the

corresponding channel (the corresponding DASTS bit in the DMA arbitration status

control register (DMSCNT) or DEN in DMA control register B for the channel

(DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when

both conditions are not satisfied.

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