SH7261 datasheet(402/1348 Pages) RENESAS

402 / 1348 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 370 of 1312

REJ09B0320-0200

11.12

Transfer Speed

Transfer speeds are calculated as shown below.

(1)

Conditions for Calculation

• DMA transfer mode: cycle-stealing transfer mode/pipelined transfer mode

• Transfer unit (one data size): properly aligned 32-bit data

• Operating clock: 60 MHz

• Number of cycles for access to external devices:

four cycles for reading; and

two cycles for writing.

(2)

Formulae Used in Calculation

• Cycle-stealing transfer mode

(data size in unit data transfer) / (number of read cycles

+ number of write cycles +

one idle cycle)

× operating clock

• Pipelined transfer mode

(data size in unit data transfer) / (whichever is larger of number of read or write cycles)

operating clock

Note:

During transfer in the pipelined transfer mode, most read and write cycles overlap.

An example of the calculation of transfer speed is given below.

(a)

Transfer between On-chip RAM

Maximum speed of transfer between on-chip RAM (0 wait) and on-chip RAM (0 wait).

• Cycle-stealing transfer mode

4 bytes / (1 read cycle

+ 1 write cycle + 1 idle cycle) × 60 MHz = 79.8 Mbytes/sec

• Pipelined transfer mode

Pipelined transfer through a single BIU is not possible. See section 11.4.1 (2), Pipelined

Transfer Mode.

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