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SH7261 Datasheet(PDF) 588 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 588 Page - Renesas Technology Corp |
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588 / 1348 page ![]() Section 12 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 Sep. 07, 2007 Page 556 of 1312 REJ09B0320-0200 12.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 12.112 shows the timing in this case. Address Write signal Compare match signal Compare match buffer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR P φ Figure 12.112 Contention between Buffer Register Write and Compare Match |
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