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SH7261 Datasheet(PDF) 590 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 590 Page - Renesas Technology Corp |
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590 / 1348 page ![]() Section 12 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 Sep. 07, 2007 Page 558 of 1312 REJ09B0320-0200 12.7.9 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 12.114 and 12.115 show the timing in this case. Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address P φ N NM Figure 12.114 Contention between TGR Read and Input Capture (Channels 0 to 4) Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address P φ M NM Figure 12.115 Contention between TGR Read and Input Capture (Channel 5) |
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