SH7261 datasheet(643/1348 Pages) RENESAS

643 / 1348 page

Section 13 8-Bit Timers (TMR)

Rev. 2.00 Sep. 07, 2007 Page 611 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

1, 0

OS[1:0]

R/W

Output Select 1 and 0*

These bits select a method of TMO pin output when

compare match A of TCORA and TCNT occurs.

00: No change when compare match A occurs

01: 0 is output when compare match A occurs

10: 1 is output when compare match A occurs

11: Output is inverted when compare match A occurs

(toggle output)

Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags.

2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first

compare match occurs after resetting.

• TCSR_1

Bit

Bit Name

Initial

Value

R/W

Description

CMFB

R/(W)*

Compare Match Flag B

[Setting condition]

• When TCNT matches TCORB

[Clearing condition]

• When writing 0 after reading CMFB = 1

CMFA

R/(W)*

Compare Match Flag A

[Setting condition]

• When TCNT matches TCORA

[Clearing condition]

• When writing 0 after reading CMFA = 1

OVF

R/(W)*

Timer Overflow Flag

[Setting condition]

• When TCNT overflows from H'FF to H'00

[Clearing condition]

• When writing 0 after reading OVF = 1

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