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SH7261 Datasheet(PDF) 647 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 647 Page - Renesas Technology Corp |
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647 / 1348 page  Section 13 8-Bit Timers (TMR) Rev. 2.00 Sep. 07, 2007 Page 615 of 1312 REJ09B0320-0200 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.4 shows the TCNT count timing for internal clock input. Figure 13.5 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values. P φ Internal clock TCNT input clock TCNT N – 1 N N + 1 Figure 13.4 Count Timing for Internal Clock Input at Falling Edge P φ External clock input pin TCNT input clock TCNT N – 1 N N + 1 Figure 13.5 Count Timing for External Clock Input at Falling and Rising Edges |
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