SH7261 datasheet(648/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 13 8-Bit Timers (TMR)

Rev. 2.00 Sep. 07, 2007 Page 616 of 1312

REJ09B0320-0200

13.5.2

Timing of CMFA and CMFB Setting at Compare Match

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the

TCOR and TCNT values match. The compare match signal is generated at the last state in which

the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT

values match, the compare match signal is not generated until the next TCNT clock input. Figure

13.6 shows this timing.

TCNT

N + 1

TCOR

Compare match

signal

CMF

Figure 13.6 Timing of CMF Setting at Compare Match

13.5.3

Timing of Timer Output at Compare Match

When a compare match signal is generated, the timer output changes as specified by bits OS3 to

OS0 in TCSR. Figure 13.7 shows the timing when the timer output is toggled by the compare

match A signal.

Compare match A

signal

Timer output pin

Figure 13.7 Timing of Toggled Timer Output at Compare Match A

SH7261 Datasheet(PDF) 648 Page - Renesas Technology Corp