SH7261 datasheet(641/1348 Pages) RENESAS

641 / 1348 page

Section 13 8-Bit Timers (TMR)

Rev. 2.00 Sep. 07, 2007 Page 609 of 1312

REJ09B0320-0200

TCR

TCCR

Channel

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Bit 1

ICKS1

Bit 0

ICKS0

Description

All



Uses external clock. Counts at rising edge*



Uses external clock. Counts at falling edge*



Uses external clock. Counts at both rising and falling

edges*

Notes: 1. If the clock input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the

TCNT_0 compare match signal, no incrementing clock is generated. Do not use this

setting.

2. To use the external clock, the function of the corresponding pin should be selected

using the pin function controller (PFC). For details, see section 25, Pin Function

Controller (PFC).

13.3.6

Timer Control/Status Register (TCSR)

TCSR displays status flags, and controls compare match output.

• TCSR_0

OS[1:0]

OS[3:2]

ADTE

OVF

CMFA

CMFB

R/(W)*R/(W)*R/(W)* R/W

R/W

Bit:

Initial value:

R/W:

Note:

* Only 0 can be written to this bit, to clear the flag.

• TCSR_1

OS[1:0]

OS[3:2]

—

OVF

CMFA

CMFB

R/(W)*R/(W)*R/(W)*

R/W

Bit:

Initial value:

R/W:

Note:

* Only 0 can be written to this bit, to clear the flag.

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