SH7261 datasheet(691/1348 Pages) RENESAS

691 / 1348 page

Section 15 Realtime Clock (RTC)

Rev. 2.00 Sep. 07, 2007 Page 659 of 1312

REJ09B0320-0200

15.3.17

RTC Control Register 2 (RCR2)

RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit

RESET, and RTC count control.

RCR2 is initialized to H'09 by a power-on reset or in deep standby mode. Bits other than the

RTCEN and START bits are initialized by a manual reset. It is not initialized in software standby

mode, and retains its contents.

R/W

Bit:

Initial value:

R/W:

PEF

PES[2:0]

RTCEN

ADJ

RESET START

Bit

Bit Name

Initial

Value

R/W

Description

PEF

R/W

Periodic Interrupt Flag

Indicates interrupt generation with the period

designated by the PES2 to PES0 bits. When set to 1,

PEF generates periodic interrupts.

0: Interrupts not generated with the period designated

by the bits PES2 to PES0.

[Clearing condition] When 0 is written to PEF

1: Interrupts generated with the period designated by

the PES2 to PES0 bits.

[Setting condition] When an interrupt is generated

with the period designated by the bits PES0 to PES2

or when 1 is written to the PEF flag

6 to 4

PES[2:0]

000

R/W

Interrupt Enable Flags

These bits specify the periodic interrupt.

000: No periodic interrupts generated

001: Periodic interrupt generated every 1/256 second

010: Periodic interrupt generated every 1/64 second

011: Periodic interrupt generated every 1/16 second

100: Periodic interrupt generated every 1/4 second

101: Periodic interrupt generated every 1/2 second

110: Periodic interrupt generated every 1 second

111: Periodic interrupt generated every 2 seconds

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