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SH7261 Datasheet(PDF) 709 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 709 Page - Renesas Technology Corp

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Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 07, 2007 Page 677 of 1312
REJ09B0320-0200
16.3.5
Serial Mode Register (SCSMR)
SCSMR specifies the SCIF serial communication format and selects the clock source for the baud
rate generator.
The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on
reset or in deep standby mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0000000000000000
RRRRRRRR
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Bit:
Initial value:
R/W:
————————
C/
A CHR
PE
O/
E STOP
—
CKS[1:0]
Bit
Bit Name
Initial
Value
R/W
Description
15 to 8
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
C/
A
0
R/W
Communication Mode
Selects whether the SCIF operates in asynchronous or
clocked synchronous mode.
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length
Selects 7-bit or 8-bit data length in asynchronous mode.
In the clocked synchronous mode, the data length is
always 8 bits, regardless of the CHR setting.
0: 8-bit data
1: 7-bit data*
Note: *
When 7-bit data is selected, the MSB (bit 7)
of the transmit FIFO data register is not
transmitted.



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