SH7261 datasheet(712/1348 Pages) RENESAS

712 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 680 of 1312

REJ09B0320-0200

16.3.6

Serial Control Register (SCSCR)

SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the

transmit/receive clock source. The CPU can always read and write to SCSCR. SCSCR is

initialized to H'0000 by a power-on reset or in deep standby mode.

00000000

RRRRRRRR

R/W

Bit:

Initial value:

R/W:

—

———————

TIE

RIE

REIE

—

CKE[1:0]

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TIE

R/W

Transmit Interrupt Enable

Enables or disables the transmit-FIFO-data-empty

interrupt (TXI) requested when the serial transmit data

is transferred from the transmit FIFO data register

(SCFTDR) to the transmit shift register (SCTSR), when

the quantity of data in the transmit FIFO register

becomes less than the specified number of

transmission triggers, and when the TDFE flag in the

serial status register (SCFSR) is set to1.

0: Transmit-FIFO-data-empty interrupt request (TXI) is

disabled

1: Transmit-FIFO-data-empty interrupt request (TXI) is

enabled*

Note: * The TXI interrupt request can be cleared by

writing a greater quantity of transmit data than

the specified transmission trigger number to

SCFTDR and by clearing TDFE to 0 after

reading 1 from TDFE, or can be cleared by

clearing TIE to 0.

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