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SH7261 Datasheet(PDF) 715 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 715 Page - Renesas Technology Corp |
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715 / 1348 page  Section 16 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 Sep. 07, 2007 Page 683 of 1312 REJ09B0320-0200 Bit Bit Name Initial Value R/W Description 2 0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of these bits, the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clocked synchronous mode, the C/ A bit in SCSMR is set to 1, and then these bits are set. • Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited • Clocked synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited |
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