SH7261 datasheet(718/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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718 / 1348 page

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 Sep. 07, 2007 Page 686 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

TEND

R/(W)* Transmit End

Indicates that when the last bit of a serial character

was transmitted, SCFTDR did not contain valid data,

so transmission has ended.

0: Transmission is in progress

[Clearing condition]

• TEND is cleared to 0 when 0 is written after 1 is

read from TEND after transmit data is written in

SCFTDR*

1: End of transmission

[Setting conditions]

• TEND is set to 1 when the chip is a power-on

reset

• TEND is set to 1 when TE is cleared to 0 in the

serial control register (SCSCR)

• TEND is set to 1 when SCFTDR does not contain

receive data when the last bit of a one-byte serial

character is transmitted

Note:

1. Do not use this bit as a transmit end flag

when the DMAC writes data to SCFTDR

due to a TXI interrupt request.

SH7261 Datasheet(PDF) 718 Page - Renesas Technology Corp