SH7261 datasheet(928/1348 Pages) RENESAS

928 / 1348 page

Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 896 of 1312

REJ09B0320-0200

20.3.1

IEBus Control Register (IECTR)

IECTR is used to control the IEB operation.

IECTR is initialized by a power-on reset or in deep standby.

76543210

Bit:

Initial value:

R/W:

00000000

R/W

—

IOL

DEE

—

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

IOL

R/W

Input/Output Level

Selects input/output pin level (polarity) for the IERxD

and IETxD pins.

0: Pin input/output is set to active low. (Logic 1 is low

level and logic 0 is high level.)

1: Pin input/output is set to active high. (Logic 1 is high

level and logic 0 is low level.)

DEE

R/W

Broadcast Receive Error Interrupt Enable

If this bit is set to 1, a reception error interrupt occurs

when the receive buffer is not in the receive enabled

state during broadcast reception (when the RE bit is not

set to 1 or the RXBSY flag is set.). At this time, the

master address is stored in IEBus reception master

address register 1 and 2.

While this bit is 0, a reception error interrupt does not

occur when the receive buffer is not in the receive

enabled state, and the reception stops and enters the

wait state. The master address is not saved.

0: A broadcast receive error is not generated up to the

control field.

1: A broadcast receive error is generated up to the

control field.

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