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SH7261 Datasheet(PDF) 924 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 924 Page - Renesas Technology Corp |
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924 / 1348 page  Section 20 IEBus TM Controller (IEB) [R5S72612] [R5S72613] Rev. 2.00 Sep. 07, 2007 Page 892 of 1312 REJ09B0320-0200 For use of active low signals, levels are reversed from the active high signals. The synchronous and data periods have approximately the same length. The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit). 20.1.5 Configuration Figure 20.5 shows the entire block configuration and table 20.6 lists the functions of each block. Transmit data buffer Peripheral bus interface IEBbus interface IEBus Receive data buffer Transmit controller Register Peripheral bus Receive controller Figure 20.5 IEB Block Diagram |
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