SH7261 datasheet(926/1348 Pages) RENESAS

926 / 1348 page

Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 894 of 1312

REJ09B0320-0200

20.2

Input/Output Pins

Table 20.7 shows the IEB pin configuration.

Table 20.7

Pin Configuration

Name

Abbreviation

I/O

Function

IEB receive data pin

IERxD

Receive data input pin

IEB transmit data pin

IETxD

Transmit data output pin

20.3

The IEB has the following registers.

Each register, in principle, has 8-bit width and is accessed in 8 bits.

Table 20.8

Abbrevi-

ation

R/W

Initial

Value

Address

Access

Size

IEBus control register

IECTR

R/W

H'00

H'FFFF1000

IEBus command register

IECMR

H'00

H'FFFF1001

IEBus master control register

IEMCR

R/W

H'00

H'FFFF1002

IEBus master unit address

IEAR1

R/W

H'00

H'FFFF1003

IEBus master unit address

IEAR2

R/W

H'00

H'FFFF1004

IEBus slave address setting

IESA1

R/W

H'00

H'FFFF1005

IEBus slave address setting

IESA2

R/W

H'00

H'FFFF1006

IEBus transmit message length

IETBFL

R/W

H'00

H'FFFF1007

IEBus reception master address

IEMA1

H'00

H'FFFF1009

IEBus reception master address

IEMA2

H'00

H'FFFF100A

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