SH7261 datasheet(929/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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929 / 1348 page

Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 897 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

R/W

Receive Enable

Enables/disables IEB reception. This bit must be set at

the initial setting before frame reception.

0: Reception is disabled.

1: Reception is enabled.

2 to 0



Reserved

These bits are always read as 0. The write value should

always be 0.

20.3.2

IEBus Command Register (IECMR)

IECMR issues commands to control IEB communications. Since this register is a write-only

IECMR is initialized by a power-on reset or in deep standby.

76543210

Bit:

Initial value:

R/W:

00000000

—————

CMD

Bit

Bit Name

Initial

Value

R/W

Description

7 to 3



All 0



Reserved

These bits are always read as 0. The write value should

always be 0.

SH7261 Datasheet(PDF) 929 Page - Renesas Technology Corp

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