SH7261 datasheet(957/1348 Pages) RENESAS

957 / 1348 page

Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 925 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

7 to 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CKS3

R/W

Input Clock Selection 3*

1*2

Specifies the clock the IEB uses

0: Peripheral clock (P

φ)

1: AUDIO_X1, AUDIO_X2



Reserved

This bit is always read as 0. The write value should

always be 0.

2 to 0

CKS[2:0]

000

R/W

Input Clock Selection 2 to 0*

Specifies the division ratio for the clock IEB uses

000: IEB uses the clock of IEB

φ specified by CKS3

(IEB

φ = 6 MHz, 6.29 MHz)

001: IEB uses the 1/2 divided clock of IEB

φ specified by

CKS3 (IEB

φ = 12 MHz, 12.58 MHz)

010: IEB uses the 1/3 divided clock of IEB

φ specified by

CKS3 (IEB

φ = 18 MHz, 18.87 MHz)

011: IEB uses the 1/4 divided clock of IEB

φ specified by

CKS3 (IEB

φ = 24 MHz, 25.16 MHz)

100: IEB uses the 1/5 divided clock of IEB

φ specified by

CKS3 (IEB

φ = 30 MHz, 31.45 MHz)

101: IEB uses the 1/6 divided clock of IEB

φ specified by

CKS3 (IEB

φ = 36 MHz, 37.74 MHz)

110: Setting prohibited

111: Setting prohibited

Notes: 1. Do not change the setting of CKS3 to CKS0 while IEBus is in transmit/receive operation

2. After the MSTP4 bit in STBCR2 is cleared to 0 to start the operation of the IEB with the

CKS3 bit set to 1 (the AUDIO_X1 and AUDIO_X2 clocks are used), do not set the

MSTP4 bit to 1 (clock supply to the IEB except IECKSR is stopped). As for the setting

of the STBCR2 register, see section 27, Power-Down Modes.

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