SH7261 datasheet(956/1348 Pages) RENESAS

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Section 20 IEBus

TM Controller (IEB) [R5S72612] [R5S72613]

Rev. 2.00 Sep. 07, 2007 Page 924 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

RXEOVEE

R/W

Overrun Control Flag Interrupt Enable

Enables/disables an overrun control flag (RXEOVE)

interrupt

0: Disables an overrun control flag (RXEOVE) interrupt

1: Enables an overrun control flag (RXEOVE) interrupt

RXERTMEE

R/W

Receive Timing Error Interrupt Enable

Enables/disables a receive timing error (RXERTME)

interrupt.

0: Disables a receive timing error (RXERTME) interrupt

1: Enables a receive timing error (RXERTME) interrupt

RXEDLEE

R/W

Overflow of Maximum Number of Receive Bytes in One

Frame Interrupt Enable

Enables/disables an overflow of the maximum number of

receive bytes in one frame (RXEDLE) interrupt

0: Disables an overflow of the maximum number of

receive bytes in one frame (RXEDLE) interrupt

1: Enables an overflow of the maximum number of

receive bytes in one frame (RXEDLE) interrupt

RXEPEE

R/W

Parity Error Interrupt Enable

Enables/disables a parity error (RXEPE) interrupt

0: Disables a parity error (RXEPE) interrupt

1: Enables a parity error (RXEPE) interrupt

20.3.20

IEBus Clock Selection Register (IECKSR)

IECKSR is an 8-bit readable/writable register that specifies the clock used in the IEB. IECKSR

can be read from or written to even when the IEB module is stopped. IECKSR is initialized by a

power-on reset or in deep standby mode.

76543210

Bit:

Initial value:

R/W:

00000000

R/W

—

CKS3

—

CKS[2:0]

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