SH7261 datasheet(1013/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

1013 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 981 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

CBUF_TS

R/W

CBUFCTL1 to CBUFCTL3 Setting Mode

0: Minutes, seconds, and frames values in BCD

1: Total number of sectors (in hexadecimal)

CBUF_Q

R/W

Q-channel code buffering data specification in the case

of a CRC error in the Q-channel code

0: The values for the last sector for which the CRC

returned a correct result are buffered.

1: The erroneous data is buffered as is.

Since subcodes are not input with this LSI, always set

this bit to 1.



R/W

Reserved

This bit is always read as 0.The write value should

always be 0.

21.3.42

Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1)

CBUFCTL1 indicates the minutes value in the header for the first sector to be buffered.

76543210

Bit:

Initial value:

R/W:

00000000

R/W

BS_MIN[7:0]

Bit

Bit Name

Initial

Value

R/W

Description

7 to 0

BS_MIN[7:0]

All 0

R/W

Setting of the minutes value in the header for the first

sector to be buffered

SH7261 Datasheet(PDF) 1013 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 1013 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL