Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SH7261 Datasheet(PDF) 1015 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 1015 Page - Renesas Technology Corp

Back Button SH7261 Datasheet HTML 1011Page - Renesas Technology Corp SH7261 Datasheet HTML 1012Page - Renesas Technology Corp SH7261 Datasheet HTML 1013Page - Renesas Technology Corp SH7261 Datasheet HTML 1014Page - Renesas Technology Corp SH7261 Datasheet HTML 1015Page - Renesas Technology Corp SH7261 Datasheet HTML 1016Page - Renesas Technology Corp SH7261 Datasheet HTML 1017Page - Renesas Technology Corp SH7261 Datasheet HTML 1018Page - Renesas Technology Corp SH7261 Datasheet HTML 1019Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 1015 / 1348 page
background image
Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 983 of 1312
REJ09B0320-0200
21.3.45
ISY Interrupt Source Mask Control Register (CROMST0M)
CROMST0M masks the ISY interrupt sources specified by the bits in the sync code status register
(CROMST0).
76543210
Bit:
Initial value:
R/W:
00000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
——
ST_
SYILM
ST_
SYNOM
ST_
BLKSM
ST_
BLKLM
ST_
SECSM
ST_
SECLM
Bit
Bit Name
Initial
Value
R/W
Description
7, 6
All 0
R/W
Reserved
These bits are always read as 0.The write value should
always be 0.
5
ST_SYILM
0
R/W
ISY interrupt ST_SYIL (bit 5 in the CROMST0 register)
source mask
4
ST_SYNOM
0
R/W
ISY interrupt ST_SYNO (bit 4 in the CROMST0
register) source mask
3
ST_BLKSM
0
R/W
ISY interrupt ST_BLKS (bit 3 in the CROMST0 register)
source mask
2
ST_BLKLM
0
R/W
ISY interrupt ST_BLKL (bit 2 in the CROMST0 register)
source mask
1
ST_SECSM
0
R/W
ISY interrupt ST_SECS (bit 1 in the CROMST0 register)
source mask
0
ST_SECLM
0
R/W
ISY interrupt ST_SECL (bit 0 in the CROMST0 register)
source mask



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com