SH7261 datasheet(1017/1348 Pages) RENESAS

1017 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 985 of 1312

REJ09B0320-0200

21.3.47

CD-ROM Decoder Reset Status Register (RSTSTAT)

RSTSTAT indicates that the RAM in the CD-ROM decoder has been cleared.

76543210

Bit:

Initial value:

R/W:

00000000

RRRRRRRR

RAM

CLRST

—

———

——

—

Bit

Bit Name

Initial

Value

R/W

Description

RAMCLRST

This bit is set to 1 on the completion of RAM clearing

triggered by setting RAMRST to 1. It is cleared by

writing a 0 to RAMRST.

6 to 0



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

21.3.48

SSI Data Control Register (SSI)

SSI provides various settings related to the data stream. For the operation corresponding to the

setting of this register, see section 21.4.1, Endian Conversion for Data in the Input Stream.

76543210

Bit:

Initial value:

R/W:

00011000

R/W

BYTEND BITEND

BUFEND0[1:0] BUFEND1[1:0]

——

Bit

Bit Name

Initial

Value

R/W

Description

BYTEND

R/W

Specifies the endian of input data from the SSI module.

When this bit is set to 1, the bytes in STRMDIN0 and

STRMDIN1 are swapped, as are those in STRMDIN2

and STRMDIN3.

BITEND

R/W

Specifies treatment of the bit order of the input data

from the SSI module.

When this bit is set to 1, the bits within each byte are

rearranged to place them in reverse order, bit 0

→ bit 7

to bit 7

→ bit 0.

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