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SH7261 Datasheet(PDF) 1020 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 1020 Page - Renesas Technology Corp |
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1020 / 1348 page ![]() Section 21 CD-ROM Decoder (ROM-DEC) Rev. 2.00 Sep. 07, 2007 Page 988 of 1312 REJ09B0320-0200 21.3.49 Interrupt Flag Register (INTHOLD) INTHOLD consists of various interrupt flags. 76543210 Bit: Initial value: R/W: 00000000 R/W R/W R/W R/W R/W R/W R/W R/W ISEC ITARG ISY IERR IBUF IREADY —— Bit Bit Name Initial Value R/W Description 7 ISEC 0 R/W ISEC Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 6 ITARG 0 R/W ITARG Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 5 ISY 0 R/W ISY Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 4 IERR 0 R/W IERR Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 3 IBUF 0 R/W IBUF Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 2 IREADY 0 R/W IREADY Interrupt Flag Writing 0 to this bit is only possible after 1 has been read from it. 1, 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. |
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