SH7261 datasheet(1022/1348 Pages) RENESAS

1022 / 1348 page

Section 21 CD-ROM Decoder (ROM-DEC)

Rev. 2.00 Sep. 07, 2007 Page 990 of 1312

REJ09B0320-0200

21.3.51

Buffer Control Register (RINGBUFCTL)

RINGBUFCTL introduces a delay in the DMA transfer request signal in order to reduce the time

period over which the CD-ROM decoder is unable to respond due to ECC correction.

Data from the CD-ROM decoder may be transferred by DMA or by the CPU; the former is

triggered by asserting the DMA transfer request signal, while the latter is driven by the IREADY

interrupt. When either the DMAC or CPU is trying to get output data for which the input data

contained errors and is thus being subjected to ECC correction, a wait will be necessary because

the CD-ROM decoder cannot respond during ECC correction.

76543210

Bit:

Initial value:

R/W:

00000000

R/W

—

DMREQDELAY

[1:0]

——

—

Bit

Bit Name

Initial

Value

R/W

Description



R/W

Reserved

This bit is always read as 0.The write value should

always be 0.

6, 5

DMREQDELAY

[1:0]

R/W

00: Assertion of the DMA transfer request signal is not

delayed.

01: Assertion of the DMA transfer request signal is

delayed by 256 cycles.

10: Assertion of the DMA transfer request signal is

delayed by 512 cycles.

11: Assertion of the DMA transfer request signal is

delayed by 1024 cycles.

4 to 0



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

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