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SH7261 Datasheet(PDF) 1021 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 1021 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 989 of 1312
REJ09B0320-0200
21.3.50
Interrupt Source Mask Control Register (INHINT)
INHINT controls masking of various interrupt requests in the CD-ROM decoder.
76543210
Bit:
Initial value:
R/W:
00000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INH
ISEC
INH
ITARG
INH
ISY
INH
IERR
INH
IBUF
INH
IREADY
PREINH
REQDM
PREINH
IREADY
Bit
Bit Name
Initial
Value
R/W
Description
7
INHISEC
0
R/W
ISEC Interrupt Mask
When set to 1, masks the generation of ISEC interrupts
6
INHITARG
0
R/W
ITARG Interrupt Mask
When set to 1, masks the generation of ITARG
interrupts
5
INHISY
0
R/W
ISY Interrupt Mask
When set to 1, masks the generation of ISY interrupts
4
INHIERR
0
R/W
IERR Interrupt Mask
When set to 1, masks the generation of IERR interrupts
3
INHIBUF
0
R/W
IBUF Interrupt Mask
When set to 1, masks the generation of IBUF interrupts
2
INHIREADY
0
R/W
IREADY Interrupt Mask
When set to 1, masks the generation of IREADY
interrupts
1
PREINH
REQDM
0
R/W
Masks setting of the DMA transfer request interrupt flag
for the output data stream.
When set to 1, the DMA transfer request interrupt
source is not retained.
0
PREINH
IREADY
0
R/W
Masks setting of the IREADY interrupt flag.
When set to 1, the interrupt source is not retained in the
IREADY flag.



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