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SH7261 Datasheet(PDF) 1026 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 1026 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 994 of 1312
REJ09B0320-0200
21.4
Operation
21.4.1
Endian Conversion for Data in the Input Stream
Stream data must be input to the core of the CD-ROM decoder in order according to the CD-ROM
data format specifications. In some systems, however, the order of the data from the SSI may have
to be changed or the data will have been padded before transfer. To cope with this, the stream data
input control section is capable of swapping the order of the data and preventing the input of
padding data to the core of the CD-ROM decoder. These functions are controlled through the SSI
data control register (SSI).
Figure 21.6 shows a case where the upper and lower 16 bits of the data, consisting of padding data
plus the first 2 bytes of sync code, that is, H'000000FF, are swapped (H'00FF0000) and input to
the CD-ROM decoder as the stream data.
Core of CD-ROM decoder
BUFEND1[1:0] = 00
BYTEND = 0
H'0000
BUFEND0[1:0] = 01
H'00FF
H'00FF
H'00FF
STRMDIN0, STRMDIN1
STRMDIN2, STRMDIN3
Figure 21.6 Example of Padded Stream Data Control by the SSI Register



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