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SH7261 Datasheet(PDF) 1030 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 1030 Page - Renesas Technology Corp

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Section 21 CD-ROM Decoder (ROM-DEC)
Rev. 2.00 Sep. 07, 2007 Page 998 of 1312
REJ09B0320-0200
(3)
Interpolated Sync Mode
In interpolated sync mode, synchronization is always driven by the internal counter after a sync
code pattern has been detected at the start of decoding. Accordingly, this mode is effective when
the sync patterns have been damaged.
However, decoding becomes incorrect after a change to the synchronization timing, since the
change in timing is not followed.
Figure 21.12 shows the operation in interpolated sync mode.
Abnormal
sector
Abnormal
sector
Abnormal
sector
Abnormal
sector
Sector 1
Intput data
Sync code
detection
Output data
Sector 1
Sector 3
Sector 4
Sector 5
Abnormal sector
Maintain
Maintain
Maintain
Maintain
Ignore
Ignore
Ignore
Figure 21.12 Operation in Interpolated Sync Mode
(4)
Interpolated Sync Plus External Sync Mode
In interpolated sync plus external sync mode, synchronization is based on the detected sync code
patterns as long as they are present, and if a sync pattern is not detected at the 2352nd byte, the
sync code maintenance is applied. Synchronization in this mode is more quickly responsive to
changes in synchronization timing than synchronization in the automatic sync maintenance mode.
However, decoding still becomes incorrect when a sync pattern is input with abnormal timing.



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