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SH7261 Datasheet(PDF) 1058 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 1058 Page - Renesas Technology Corp |
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1058 / 1348 page ![]() Section 22 A/D Converter (ADC) Rev. 2.00 Sep. 07, 2007 Page 1026 of 1312 REJ09B0320-0200 6. The ADST bit is not cleared automatically, so steps 2. to 4. are repeated as long as the ADST bit remains set to 1. When steps 2. to 4. are repeated, the ADF flag is kept to 1. When the ADST bit is cleared to 0, A/D conversion stops. The ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit. If both the ADF flag and ADIE bit are set to 1 while steps 2. to 4. are repeated, an ADI interrupt is requested at all times. To generate an interrupt on completing conversion of the third channel, clear the ADF bit to 0 after an interrupt is requested. |
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