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SH7261 Datasheet(PDF) 1061 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 1061 Page - Renesas Technology Corp |
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1061 / 1348 page ![]() Section 22 A/D Converter (ADC) Rev. 2.00 Sep. 07, 2007 Page 1029 of 1312 REJ09B0320-0200 (1) (2) P φ ADIF t D t SPL t CONV Write signal Input sampling timing (1): (2): t D: t SPL: t CONV: [Legend] Address ADCSR write cycle ADCSR address A/D conversion start delay time Input sampling time A/D conversion time Figure 22.5 A/D Conversion Timing Table 22.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time t D 11 — 14 19 — 26 35 — 50 Input sampling time t SPL — 33 — — 65 — — 129 — A/D conversion time t CONV 135 — 138 267 — 274 531 — 546 Note: Values in the table are the numbers of states. |
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