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SH7261 Datasheet(PDF) 1062 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 1062 Page - Renesas Technology Corp |
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1062 / 1348 page  Section 22 A/D Converter (ADC) Rev. 2.00 Sep. 07, 2007 Page 1030 of 1312 REJ09B0320-0200 Table 22.5 A/D Conversion Time (Multi Mode and Scan Mode) CKS1 CKS0 Conversion Time (States) 0 128 (constant) 0 1 256 (constant) 1 0 512 (constant) Note: Values in the table are the numbers of states. 22.4.6 External Trigger Input Timing A/D conversion can also be externally triggered. When the TRGS[3:0] bits in ADCSR are set to B'1001, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, regardless of the operating mode, are the same as when the ADST bit has been set to 1 by software. Figure 22.6 shows the timing. P φ ADST A/D conversion ADTRG Internal trigger signal Figure 22.6 External Trigger Input Timing |
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