SH7261 datasheet(1060/1348 Pages) RENESAS

1060 / 1348 page

Section 22 A/D Converter (ADC)

Rev. 2.00 Sep. 07, 2007 Page 1028 of 1312

REJ09B0320-0200

22.4.4

A/D Converter Activation by External Trigger, MTU2, or TMR

The A/D converter can be independently activated by an A/D conversion request from the external

trigger, MTU2, or TMR. To activate the A/D converter by the external trigger, MTU2, or TMR,

set the A/D trigger enable bits (TRGS[3:0]). After this bit setting has been made, the ADST bit is

automatically set to 1 and A/D conversion is started when an A/D conversion request from the

external trigger, MTU2, or TMR occurs. The channel combination is determined by the CH[2:0]

bits in ADCSR. The timing from setting of the ADST bit until the start of A/D conversion is the

same as when 1 is written to the ADST bit by software.

22.4.5

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at the A/D conversion start delay time (t

D) after the ADST bit in ADCSR is set to 1, then

starts conversion. Figure 22.5 shows the A/D conversion timing. Table 22.4 indicates the A/D

conversion time.

As indicated in figure 22.5, the A/D conversion time (t

CONV) includes tD and the input sampling

time(t

SPL). The length of tD varies depending on the timing of the write access to ADCSR. The total

conversion time therefore varies within the ranges indicated in table 22.4.

In multi mode and scan mode, the values given in table 22.4 apply to the first conversion. In the

second and subsequent conversions, time is the values given in table 22.5.

SH7261 Datasheet(PDF) 1060 Page - Renesas Technology Corp