SH7261 datasheet(1076/1348 Pages) RENESAS

1076 / 1348 page

Section 24 I/O Ports

Rev. 2.00 Sep. 07, 2007 Page 1044 of 1312

REJ09B0320-0200

24.1.1

Table 24.1 lists the port A registers.

Table 24.1

Abbreviation

R/W

Address

Access Size

Port A data register H

PADRH

R/W

H'FFFE3800

8, 16, 32

Port A data register L

PADRL

R/W

H'FFFE3802

8, 16

Port A port register H

PAPRH

H'FFFE3804

8, 16, 32

Port A port register L

PAPRL

H'FFFE3806

8, 16

24.1.2

Port A Data Registers H and L (PADRH and PADRL)

PADRH and PADRL are 16-bit readable/writable registers that store port A data. Bits PA31DR to

PA0DR correspond to pins PA31 to PA0, respectively.

If a pin is set to the general output function, the pin will output the value written to the

corresponding bit in PADRH or PADRL, and the register value is read from PADRH or PADRL

regardless of the state of the pin.

If a pin is set to the general input function, the pin state, not the register value, will be returned if

PADRH or PADRL is read. Also, if a value is written to PADRH or PADRL, although the value

will actually be written, it will have no influence on the state of the pin. Table 24.2 summarizes

the PADRH and PADRL read/write operations.

PADRH and PADRL are initialized to H'0000 by a power-on reset or in deep standby mode.

These registers are not initialized either by a manual reset or by switching to sleep mode or

software standby mode.

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