SH7261 datasheet(133/1348 Pages) RENESAS

133 / 1348 page

Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 101 of 1312

REJ09B0320-0200

5.2

Resets

5.2.1

Input/Output Pins

Table 5.5 shows the configuration of pins relating to the resets.

Table 5.5

Pin Configuration

Pin Name

Symbol

I/O

Function

Power-on reset

RES

Input

When this pin is driven low, this LSI shifts to the power-on

reset processing

Manual reset

MRES

Input

When this pin is driven low, this LSI shifts to the manual

reset processing.

5.2.2

Types of Reset

A reset is the highest-priority exception handling source. There are two kinds of resets, power-on

and manual. As shown in table 5.6, the CPU state is initialized by both a power-on reset and a

manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip

peripheral module registers except a few registers are initialized by a power-on reset, but not by a

manual reset.

Table 5.6

Reset States

Conditions for Transition to Reset State

Internal States

Type

RES H-UDI Command MRES

WDT

Overflow

CPU

On-Chip

Peripheral

Modules, I/O Port

WRCSR of

WDT, FRQCR

of CPG

Low

—

Initialized

Initialized*

Initialized

High

H-UDI reset assert

command is set

—

Initialized

Initialized*

Initialized

Power-on

reset

High

Command other

than H-UDI reset

assert is set

—

Power-on

reset

Initialized

Initialized*

Not initialized

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