SH7261 datasheet(135/1348 Pages) RENESAS

135 / 1348 page

Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 103 of 1312

REJ09B0320-0200

(2)

Power-On Reset by Means of H-UDI Reset Assert Command

When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on

reset by means of an H-UDI reset assert command is equivalent to power-on reset by means of the

RES pin. Setting the H-UDI reset negate command cancels the power-on reset state. The time

required between an H-UDI reset assert command and H-UDI reset negate command is the same

as the time to keep the

RES pin low to initiate a power-on reset. In the power-on reset state

generated by an H-UDI reset assert command, setting the H-UDI reset negate command starts

power-on reset exception handling. The CPU operates in the same way as when a power-on reset

was caused by the

RES pin.

(3)

Power-On Reset Initiated by WDT

When a setting is made for a power-on reset to be generated in the WDT’s watchdog timer mode,

and WTCNT of the WDT overflows, this LSI enters the power-on reset state.

In this case, WRCSR of the WDT and FRQCR of the CPG are not initialized by the reset signal

generated by the WDT.

If a reset caused by the

RES pin or the H-UDI reset assert command occurs simultaneously with a

reset caused by WDT overflow, the reset caused by the

RES pin or the H-UDI reset assert

command has priority, and the WOVF bit in WRCSR is cleared to 0. When power-on reset

exception processing is started by the WDT, the CPU operates in the same way as when a power-

on reset was caused by the

RES pin.

SH7261 Datasheet(PDF) 135 Page - Renesas Technology Corp