SH7261 datasheet(139/1348 Pages) RENESAS

139 / 1348 page

Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 107 of 1312

REJ09B0320-0200

5.5

5.5.1

(1)

Bank Overflow

In the state where saving has already been performed to all register bank areas, bank overflow

occurs when acceptance of register bank overflow exception has been set by the interrupt

controller (the BOVE bit in IBNR of the INTC is set to 1) and an interrupt that uses a register

bank has occurred and been accepted by the CPU.

(2)

Bank Underflow

Bank underflow occurs when an attempt is made to execute a RESBANK instruction while saving

has not been performed to register banks.

5.5.2

When a register bank error occurs, register bank error exception handling starts. The CPU operates

as follows:

1. The exception service routine start address which corresponds to the register bank error that

occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction for a bank overflow, and the start

address of the executed RESBANK instruction for a bank underflow.

To prevent multiple interrupts from occurring at a bank overflow, the interrupt priority level

that caused the bank overflow is written to the interrupt mask level bits (I3 to I0) of the status

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

SH7261 Datasheet(PDF) 139 Page - Renesas Technology Corp