SH7261 datasheet(138/1348 Pages) RENESAS

138 / 1348 page

Section 5 Exception Handling

Rev. 2.00 Sep. 07, 2007 Page 106 of 1312

REJ09B0320-0200

5.3.2

Address Error Exception Handling

When an address error occurs, address error exception handling starts after the bus cycle in which

the address error occurred ends and execution of the instruction being executed completes. The

CPU operates as follows.

1. The exception service routine start address which corresponds to the address error that

occurred is fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

5.4

Bus Error

5.4.1

Bus Error Generation Source

In bus monitor, notification of bus error occurrence to the CPU can be set. The notification is

generated when incorrect address access or bus timeout is detected. For details, see section 10,

Bus Monitor.

5.4.2

Bus Error Exception Handling

When a bus error occurs, bus error exception handling starts after the bus cycle in which the bus

error occurred ends and execution of the instruction being executed completes. The CPU operates

as follows.

1. The exception service routine start address which corresponds to the bus error that occurred is

fetched from the exception handling vector table.

2. The status register (SR) is saved to the stack.

3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the last executed instruction.

4. After jumping to the address fetched from the exception handling vector table, program

execution starts. The jump that occurs is not a delayed branch.

SH7261 Datasheet(PDF) 138 Page - Renesas Technology Corp