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SH7261 Datasheet(PDF) 140 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 140 Page - Renesas Technology Corp |
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140 / 1348 page ![]() Section 5 Exception Handling Rev. 2.00 Sep. 07, 2007 Page 108 of 1312 REJ09B0320-0200 5.6 Interrupts 5.6.1 Interrupt Sources Table 5.8 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules. Table 5.8 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller (UBC) 1 H-UDI User debugging interface (H-UDI) 1 IRQ IRQ0 to IRQ7 pins (external input) 8 PINT PINT0 to PINT7 pins (external input) 8 A/D converter (ADC) 1 CD-ROM decoder (ROM-DEC) 6 Multifunction timer pulse unit 2 (MTU2) 28 Realtime clock (RTC) 3 Watchdog timer (WDT) 1 I²C bus interface 3 (IIC3) 15 Direct memory access controller (DMAC) 9 Serial communication interface with FIFO (SCIF) 32 Controller area network (RCAN-ET) 2 IEBus TM controller (IEB) 1 Serial sound interface (SSI) 2 On-chip peripheral module 8-bit timer (TMR) 6 Each interrupt source is allocated a different vector number and vector table offset. See table 6.4 in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table address offsets. |
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