SH7261 datasheet(165/1348 Pages) RENESAS

165 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 133 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

3 to 0

BN[3:0]*

0000

Bank Number

These bits indicate the bank number to which saving is

performed next. When an interrupt using register banks

is accepted, saving is performed to the register bank

indicated by these bits, and BN is incremented by 1.

After BN is decremented by 1 due to execution of a

RESBANK (restore from register bank) instruction,

restoration from the register bank is performed.

Note:

Bits BN[3:0] are initialized at a manual reset.

6.3.10

DMA Transfer Request Enable Register 0 (DREQER0)

DMA transfer request enable register 0 (DREQER0) is an 8-bit readable/writable register that

enables/disables the IIC3 DMA transfer requests, and enables/disables CPU interrupt requests.

DMA transfer request enable register 0 is initialized by a power-on reset or in deep standby mode.

R/W

Reserved

IIC3

2ch TX

IIC3

2ch RX

IIC3

1ch TX

IIC3

1ch RX

IIC3

0ch TX

IIC3

0ch RX

Bit:

Initial value:

R/W:

Bit

Bit Name

Initial

Value

R/W

Description

Reserved

R/W

Reserved

R/W

IIC3 2ch TX

R/W

IIC3 2ch RX

R/W

IIC3 1ch TX

R/W

IIC3 1ch RX

R/W

IIC3 0ch TX

R/W

IIC3 0ch RX

R/W

DMA Transfer Request Enable Bits

These bits enable/disable DMA transfer requests, and

enable/disable CPU interrupt requests.

0: DMA transfer request disabled, CPU interrupt

request enabled

1: DMA transfer request enabled, CPU interrupt request

disabled

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